1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, the invention relates to a PRAM performing program loop operations and a method of programming same.
2. Description of the Related Art
Semiconductor memory devices may be classified random access memory (RAM) devices and read only memory (ROM) devices. ROM is typically implemented as a nonvolatile memory that retains stored data when power is not applied. Examples of ROM are Programmable ROM (PROM), Erasable PROM (EPROM), Electrically EPROM (EEPROM), Flash Memory, etc. Flash memory may be further classified as NOR flash memory and a NAND flash memory.
RAM has conventionally been implemented in volatile memory that looses stored data when power is no longer applied. Examples of RAM include Dynamic RAM (DRAM) and Static RAM (SRAM).
Many emerging memory devices seek to replace the capacitor element conventionally associated with a DRAM with a nonvolatile material. Examples of such devices include the Ferroelectric RAM (FRAM) which uses a ferroelectric capacitor, the magnetic RAM (MRAM) which uses a tunneling magneto-resistive (TMP) layer, and the Phase change RAM which uses a material such as chalcogenide alloys to implement a data storage element having changeable material states.
Thus, PRAM is a nonvolatile memory device that uses a changeable phase state (e.g., a resistance property) which is response to an applied temperature condition. Thus far, the PRAM has manifest an ability to be manufactured using a relatively simple (low cost) process and may be used to implement high-capacity memory devices.
Figure (FIG.) 1 is a schematic diagram of a memory cell in a PRAM. Referring to FIG. 1, a memory cell 10 includes a memory element 11, and a select element 12. Memory element 11 is connected between a bit line BL and select element 12. Select element 12 is gated by a word line and is connected between memory element 11 and ground.
Memory element 11 may be implemented with a phase change material, such as GST. The phase change material may be placed in a crystalline state or an amorphous state by applying different temperature conditions. In current practice, the state of the phase change material is defined by the application of a heating current through the bit line BL. Thus, the PRAM programs data in relation to the material state properties of certain phase change materials such as GST.
Select element 12 may be implemented by an NMOS transistor (NT). The word line WL is connected to the gate of the NMOS transistor NT. When a predetermined voltage is applied to the word line WL, the NMOS transistor NT is turned ON. When the NMOS transistor NT is turned ON, memory element 11 receives a current through the bit line BL. Referring to FIG. 1, memory element 11 is connected between the bit line BL and the select element 12. However, select element 12 may be alternately be connected between the bit line BL and the memory element 11.
FIG. 2 is another schematic diagram of an alternate PRAM implementation. Referring to FIG. 2, a memory cell 20 includes a memory element 21 and a select element 22. Memory element 21 is connected between the bit line BL and select element 22, and select element 22 is connected between memory element 21 and ground. Memory element 21 may be identical to memory element 11 of FIG. 1.
However, select element 22 may be alternately implemented using a diode D. Memory element 21 is connected to the anode of the diode D, and the word line WL is connected to its cathode. When a voltage difference between the anode and the cathode of the diode D is higher then its threshold voltage, the diode D is turned ON. When the diode is turned ON, memory element 21 is supplied with current through the bit line BL.
FIG. 3 is a graph illustrating the material phase state characteristics of an exemplary phase change material (e.g., GST) as a function of respective temperature conditions. Referring to FIG. 3, one phase state for the phase change material is termed the amorphous state (1). Another phase state for the phase change material is termed the crystalline state (2).
Referring to FIG. 3, the phase change material assumes the amorphous state by being quickly quenched after being heated above its melting temperature Tm over a relatively short period of time T1. The amorphous state is commonly associated with a “reset” state or a stored data value of 1.
In contrast, the phase change material assumes the crystalline state by being cooled at a relatively slow rate over a time period T2 (longer then T1) after being heated above its crystallization temperature Tc (lower than the melting temperature Tm). The crystalline state is commonly associated with a “set” state or a stored data value of 0. In the PRAM, the resistance of the memory cell will vary with its material state (i.e., a relatively high resistance in the amorphous state and a relatively low resistance in the crystalline state).
Conventional PRAMs include a write driver circuit supplying a program current to the phase change material of constituent memory cell(s) during a program operation. The write driver circuit supplies the program current, (i.e., either a set current or a reset current) to one or more selected cells in relation to an externally provided supply voltage (e.g., 2.5 V). When applied through the phase change material of the selected memory cell(s), the set current will induce a temperature condition that places the phase change material into its set state. In similar vein, the reset current will place the phase change material into the set state.
In order to improve programming reliability, the PRAM performs a program verify operation as part of the program operation. In general, the PRAM runs iterative programming loop that increases the program current on a step by step basis while performing the program and program verify operations.
During each program loop, the program verify operation is performed following a program operation. According to a program verification result obtained by the program verify operation, the program current is increased when memory cell programming fails. Following this increase in program current, another program loop operation is run. This iterative loop continues until the selected memory cell(s) are properly programmed (a “pass” condition).
This iterative programming loop approach improves the reliability of program data. On the other hand, the iterative program loop approach lengthens the overall programming time. Moreover, the life-time durability of the constituent memory cells is reduced by the repeated application of a programming current over numerous programming loop operations. Finally, a relatively large amount of power may be consumed using the programming loop approach.